The present invention relates in general to voltage translator circuits, and more particularly, to a voltage level translator circuit with cascoded transistors.
Voltage level translator circuits are commonly used in digital design to convert a data signal from one voltage level to another voltage level that represents the same logic state. For example, in 0.5 sub-micron MOS technology, the voltage level for a logic one is typically 3.3 volts because of the lower power supply voltage. In higher micron MOS technology the voltage level for a logic one is 5.0 volts in accordance with its higher power supply voltage. In order to transition from one technology to another, it is necessary to level shift the voltage of the data signal to match the logic levels of the receiving technology.
In the prior art, level shifting diodes are commonly used to translate from one voltage level to another voltage level representing the same logic state. The diodes are stacked anode to cathode to achieve the desired level shifting. A problem occurs in that some of the level shifting transistors have the full higher power supply voltage across their gate oxide layer. In sub-micron MOS technology, the gate oxide layer cannot handle the higher voltage stresses.
Hence, a need exists to translate voltage levels in sub-micron MOS technologies without overstressing the gate oxide layers.